The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of integrated circuit evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased.
The need for small geometry sizes places stricter demands on a photolithography process. In particular, the alignment between various layers in the semiconductor device (also referred to as overlay) needs to be precise and accurate. In other words, it is desirable to reduce overlay errors. Overlay marks (overlay patterns) may be used to measure the overlay error on wafers patterned by a photolithography tool. The size of the measured overlay error corresponds to the quality of the lens in the photolithography tool used to pattern the wafer. As geometry sizes become increasingly small, existing overlay marks and existing methods to characterize the quality of photolithography tool lenses may not be sufficient. Thus, lens quality assessments may be skewed, which may lead to more chip failures.
Therefore, while existing overlay marks and lens quality characterization methods have been generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect.